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rt9703 1 ds9703-09 april 2011 www.richtek.com features pin configurations applications 80m , 3a smart universal power switch with flag general description the rt9703 is a low voltage, high performance single n-mosfet power switch, designed for power rail on/off control with low r ds(on) 80m and full protection functions. the rt9703 equipped with a charge pump circuitry to drive the internal mosfet switch and a flag output is available to indicate fault conditions against large di/dt which may cause the supply to fall out of regulation. in order to fit different application, an ip pin is offered for current limit point setting, a resistor from ip to ground sets the current limit for the switch. additional features include soft-start to limit inrush current during plug-in, thermal shutdown to prevent catastrophic switch failure from high-current loads, under-voltage lockout (uvlo) to ensure that the device remains off unless there is a valid input voltage present, a precision resistor-programmable output current limit up to 3.5a. besides, the lower quiescent current as 30 a making this device ideal for portable battery-operated equipment. the rt9703 is available in sop-8 package requiring minimum board space and smallest components. ordering information z lcd monitor, lcd-tv z usb power module for adsl z information appliance and set-top box z battery-powered equipment z hot-plug power supplies z acpi power distribution z pci bus power switching z motherboard & notebook pcs z pc card hot swap application z z z z z adjustable current limiting up to 3.5a z z z z z built-in (typically 80m ) n-mosfet z z z z z reverse current flow blocking (no body diode) i.e. output can be forced higher than input (off-state) z z z z z low supply current : ` ` ` ` ` 30 a typical at switch on state ` ` ` ` ` less than 1 a typical at switch off state z z z z z guaranteed 3a continuous load current z z z z z wide input voltage ranges : 2v to 5.5v z z z z z open-drain fault flag output z z z z z hot plug-in application (soft-start) z z z z z 1.7v typical under-voltage lockout (uvlo) z z z z z thermal shutdown protection z z z z z smallest sop-8 package minimizes board space z z z z z rohs compliant and 100% lead (pb)-free (top view) sop-8 flg vout vout gnd en vin vin ip 2 3 4 5 8 7 6 note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. rt9703 package type s : sop-8 lead plating system p : pb free g : green (halogen free and pb free)
rt9703 2 ds9703-09 april 2011 www.richtek.com function block diagram typical application circuit functional pin description pin name pin function vin power input voltage. vout output voltage. gnd ground. en chip enable (active high). flg open-drain fault flag output. ip current limit programming input. vin en flg ip vout gnd rt9703 peripheral + 33f r set pull-up resistor (10k to 100k) supply voltage 10f fault flag chip enable gate control output voltage detection delay oscillator uvlo charge pump bias thermal protection flg vout en + - + - ip vin v ref
rt9703 3 ds9703-09 april 2011 www.richtek.com test circuits note: above test circuits reflected the graphs shown on ? typical operating characteristics ? are as follows: 1 ? turn-on rising & turn-off falling time vs. temperature, turn-on & off response, flag response at chip enable, flag response (enable into current limit) 2 ? on-state & off-state supply current vs. input voltage/temperature, turn-off leakage current vs. temperature 3 ? on-resistance vs. input voltage/temperature 4 ? en threshold voltage vs. input voltage/temperature, flag delay time vs. input voltage/temperature, uvlo threshold vs. temperature, uvlo at rising & falling 5 ? current limit vs. input voltage/temperature/r set , current limit factor vs. r set , short circuit current vs. input voltage, inrush current response, soft-start response, current-limit & short circuit with thermal shutdown, short-circuit response 12 34 5 vin en flg vout gnd rt9703 + + r l a c out i l v out r fg c in v in ip r set i supply a i out s1 v flg chip enable vin en flg vout gnd rt9703 + a a ip i leakage r l r set v in c in i supply chip enable vin en flg vout gnd rt9703 + + i out c out v rds(on) c in v in v ip r set vin en flg vout gnd rt9703 + + r l c out i l v out r fg c in v in v ce ip r set v flg vin en flg vout gnd rt9703 + + r l a i out s3 c out i l v out c in v in s2 ip r set
rt9703 4 ds9703-09 april 2011 www.richtek.com electrical characteristics recommended operating conditions (note 3) z supply input voltage ------------------------------------------------------------------------------------------------ 2v to 5.5v z chip enable input voltage ----------------------------------------------------------------------------------------- 0v to 5.5v z junction temperature range -------------------------------------------------------------------------------------- ? 20 c to 100 c (v in = 5v, c in = c out = 1 f, t a = 25c, unless otherwise specified) absolute maximum ratings (note 1) z supply v oltage ------------------------------------------------------------------------------------------------------- 6.5v z chip enable input v oltage ----------------------------------------------------------------------------------------- ? 0.3v to 6.5v z flag v oltage ----------------------------------------------------------------------------------------------------------- 6.5v z power dissipation, p d @ t a = 25 c sop-8 ------------------------------------------------------------------------------------------------------------------ 0.95w z package thermal resistance sop-8, ja ------------------------------------------------------------------------------------------------------------ 104 c/w z junction temperature ----------------------------------------------------------------------------------------------- 125 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 2) hbm (human body mode) ----------------------------------------------------------------------------------------- 8kv mm (machine mode) ------------------------------------------------------------------------------------------------ 800v parameter symbol test conditions min typ max unit switch on resistance r ds(on) i out = 3a (note 8) -- 80 100 m i sw_on switch on, v out = open -- 30 50 supply current i sw_off switch off, v out = open -- 0.1 1 a logic-low voltage v il switch off -- -- 0.8 v ce threshold (note 7) logic-high voltage v ih switch on 2.0 -- -- v ce input current i ce v ce = 0v to 5.5v -- 0 -- a output leakage current i leakage v ce = 0v, r load = 0 -- 0.5 10 a output turn-on rise time t on_rise 10% to 90% of v out rising -- 1.5 -- ms current limit factor (note 5) i lim x r set -- 210k -- a ? max. current limit setting (note 6) i limset v in = 3.3v to 5.5v, r set = 60k -- -- 3.5 a current limit setting accuracy i lim set i limset = 0.5a to 3a (r set = 420k to 70k ) ? 20 -- +20 % flag output resistance r flg i sink = 1ma -- 15 400 flag off current i flg_off v flg = 5v -- 0.01 1 a flag delay time (note 4) t d form fault condition to flg assertion 2 4.6 8 ms under-voltage lockout v uvlo v in increasing 1.3 1.7 -- v under-voltage hysteresis v uvlo v in decreasing -- 0.1 -- v
rt9703 5 ds9703-09 april 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. the flag delay time is input voltage dependent, see ? typical operating characteristics ? graph for further details. note 5. current limit is determined by: i limit = 210k/r set , where r set is in ohms. note 6. it is important to note that the maximum current limit value shall be set properly in accordance with its supply voltage otherwise which it may result in the failure occurrence. see ? maximum current limit vs. supply voltage ? graph shown on the applications information section for further details. note 7. for input voltage lower than 5v, the threshold level will subject to 0.6v deviation throughout the operating junction temperature range. refer to the ? typical operating characteristics ? graph for further details. note 8. r ds(on) is measured at constant junction temperature by using a 1ms current pulse. parameter symbol test conditions min typ max unit thermal shutdown protection t sd -- 130 -- c thermal shutdown hysteresis t sd -- 10 -- c
rt9703 6 ds9703-09 april 2011 www.richtek.com typical operating characteristics on-state supply current vs. input voltage 10 15 20 25 30 35 40 45 50 1.522.533.544.555.5 input voltage (v) supply current (ua) a v en = 5v c in = 10 f r l = open r set = 100k 2 off-state supply current vs. input voltage -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 1.522.533.544.555.5 input voltage (v) supply current (ua) a v en = 5v c in = 10 f c out = 33 f r l = open 2 on-state supply current vs. temperature 10 15 20 25 30 35 40 45 50 -40-20 0 20406080100120 temperature supply current (ua) a v in = v en = 5v c in = 10 f c out = 33 f r l = open r set = 100k ( c) 2 off-state supply current vs. temperature -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -40-20 0 20406080100120 temperature supply current (ua) a v in = 5v, v en = 0v c in = 10 f c out = 33 f r l = open r set = 100k ( c) 2 current limit vs. input voltage 1.6 1.7 1.8 1.9 2 2.1 22.533.5 44.555.5 input voltage (v) current limit (a) c in = 10 f, c out = 33 f r l = 0.5 , r set = 116k s2 = on, s3 = off 5 current limit vs. temperature 1.6 1.7 1.8 1.9 2 2.1 -40-20 0 20406080100120 temperature current limit (a) v in = 5v c in = 10 f, c out = 33 f r l = 0.5 , r set = 116k s2 = on, s3 = off ( c) 5
rt9703 7 ds9703-09 april 2011 www.richtek.com on-resistance vs. input voltage 62 63 64 65 66 67 68 69 70 22.533.544.555.5 input voltage (v) on-resistance (m ? ) 3 i out = 0.5a, r set = 50k c in = 10 f, c out = 33 f current limit vs. r set 0 0.5 1 1.5 2 2.5 3 3.5 4 50 100 150 200 250 300 350 400 450 500 r set (k ) current limit (a) v in = 5v, r l = 0.5 c in = 10 f, c out = 33 f s2 = on, s3 = off 5 ce threshold voltage vs. input voltage 0 0.4 0.8 1.2 1.6 2 2.4 22.5 33.5 44.5 55.5 input voltage (v) ce threshold voltage (v) c in = 10 f, c out = 33 f i l = 100ma, r set = 100k 4 en en pin threshold voltage vs. input en pin threshold voltage (v) inrush current response time (5ms/div) c out = 1000 f v in = 5v, c in = 10 f r l = 0.5 , r set = 175k , s2 = on, s3 = off c out = 470 f c out = 1 f 5 (1a/div) short circuit current response time (10ms/div) v out (5v/div) i out (0.5a/div) v in = 5v, c in = 10 f, c out = 0.1 f r set = 175k , s2 = s3 = on 5 on-resistance vs. temperature 48 58 68 78 88 -40 -20 0 20 40 60 80 100 120 temperature on-resistance (m ? ) ( c) 3 i out = 0.5a, r set = 50k c in = 10 f, c out = 33 f v in = 5v
rt9703 8 ds9703-09 april 2011 www.richtek.com ce threshold voltage vs. temperature 0 0.4 0.8 1.2 1.6 2 2.4 -40 -20 0 20 40 60 80 100 120 temperature ce thresold voltage (v) ( c) v in = 5v, i l = 100mv c in = 10 f, c out = 33 f r set = 100k 4 en pin threshold voltage vs. en pin threshold voltage (v) turn-off falling time vs. temperature 0 1 2 3 4 5 6 -40-20 0 20406080100120 temperature turn-off falling time (us) ( c) v in = 5v, v en = 0v c in = 10 f, c out = 1 f r l = 30 , r set = 200k s 1 = on 1 flag dealy time vs. input voltage 0 2 4 6 8 10 22.533.5 44.555.5 input voltage (v) flag delay time (ms) v en = 5v c in = 10 f, c out = 33 f r l = 0.5 , r set = 100k r fg = 1k 4 turn-on rising time vs. temperature 0 0.5 1 1.5 2 2.5 3 3.5 4 -40-20 0 20406080100120 temperature turn-on rising time (ms) v in = v en = 5v c in = 10 f, c out = 1 f r l = 30 , r set = 200k s1 = on ( c) 1 turn-off leakage current vs. temperature -0.3 -0.2 -0.1 0 0.1 0.2 0.3 -40-20 0 20406080100120 temperature turn-off leakage current (ua) a v in = 5v, v en = 0v c in = 10 f, c out = 33 f r l = 0 , r set = 100k ( c) 2 flag delay time vs. temperature 4 5 6 7 8 9 -40 -20 0 20 40 60 80 100 120 temperature flag delay time (ms) ( c) v in = v en = 5v c in = 10 f, c out = 33 f r l = 0.5 , r set = 100k r fg = 1k 4
rt9703 9 ds9703-09 april 2011 www.richtek.com uvlo threshold vs. temperature 0 0.5 1 1.5 2 2.5 3 3.5 -40-20 0 20406080100120 temperature uvlo threshold (v) ( c) c in = 10 f, c out = 33 f r l = 1k , r set = 100k 4 uvlo at falling time (25ms/div) v in (1v/div) v out (1v/div) v in = v en = 5v c in = 1000 f, c out = 1 f r l = 30 , r set = 200k 4 uvlo at rising time (1ms/div) v in (1v/div) v out (1v/div) v in = v en = 5v c in = 1000 f, c out = 1 f 4 flag response when enable into current limit time (1ms/div) v flg (5v/div) v en (5v/div) v in = 5v c in = 1 f, c out = 33 f r l = 0.5 , r set = 175k i l (1a/div) 1 turn-on response time (250 s/div) v en (5v/div) v out (1v/ v in = 5v, s1 = on c in = 10 f, c out = 1 f r l = 33 , r set = 200k 1 turn-off response time (100 s/div) v en (5v/div) v out (5v/div) v in = 5v, s1 = off c in = 10 f, c out = 1 f r l = 30 , r set = 200k i l (100ma/div) 1
rt9703 10 ds9703-09 april 2011 www.richtek.com flag response at chip enable time (10ms/div) v flg (5v/div) v en (5v/div) v in = 5v c in = 1 f, c out = 33 f r l = 0.5 , r set = 420k i l (0.5a/div) 1 current limit with thermal shutdown time (50ms/div) v en (5v/div) i l (1a/div) v in = 5v c in = 10 f c out = 33 f r l = 0.5 , r set = 116k s2 = on, s3 = off 5 soft-start response with current limit time (1ms/div) v en (5v/div) i l (2a/div) v out (5v/div) c in = 10 f, c out = 1 f r l = 0.5 , r set = 70k 5 v in (5v/div) short- circuit with thermal shutdown time (10ms/div) v trigger (5v/div) i l (0.5a/div) v in = 5v, c in = 10 f, c out = 33 f r set = 140k , s2 = on, s3 = on 5
rt9703 11 ds9703-09 april 2011 www.richtek.com applications information the rt9703 is a high-side, n-channel, power switch available with active high enable input. low r ds(on) dd 80m and full protection functions make it optimized to replace complex discrete on/off control circuitry. input and output v in (input) is the power source connection to the internal circuitry and the drain of the mosfet. v out (output) is the source of the mosfet. in a typical application, current flows through the switch from v in to v out toward the load. if v out is greater than v in , current will flow from v out to v in since the mosfet is bidirectional when on. unlike a normal mosfet, there is no a parasitic body diode between drain and source of the mosfet, the rt9703 prevents reverse current flow if v out being externally forced to a higher voltage than v in when the output disabled (v en < 0.8v). chip enable input the switch will be disabled when the en pin is in a logic low condition. during this condition, the internal circuitry and mosfet are turned off, reducing the supply current to 0.1 a typically. the maximum guaranteed voltage for a logic low at the en pin is 0.8v. a minimum guaranteed voltage of 2v at the en pin will turn the rt9703 back on. floating the input may cause unpredictable operation. en should not be allowed to go negative with respect to gnd. the en pin may be directly tied to v in to keep the part on. soft-start for hot plug-in applications in order to eliminate the upstream voltage droop caused by the large inrush current during hot-plug events, the ? soft-start ? feature effectively isolates the power source from extremely large capacitive loads. fault flag the rt9703 provides a flg signal pin which is an n-channel open drain mosfet output. this open drain output goes low when v out < v in ? 1v, current limit or the die temperature exceeds 130 c approximately. the flg output is capable of sinking a 10ma load to typically 150mv above ground. the flg pin requires a pull-up resistor, this resistor should be large in value to reduce energy drain. a 100k pull-up resistor works well for most applications. in the case of an over-current condition, flg will be asserted only after the flag response delay time, t d , has elapsed. this ensures that flg is asserted only upon valid over-current conditions and that erroneous error reporting is eliminated. for example, false over-current conditions may occur during hot-plug events when a highly large capacitive load is connected and causes a high transient inrush current that exceeds the current limit threshold. the flg response delay time t d is typically 4.6ms. under-voltage lockout under-voltage lockout (uvlo) prevents the mosfet switch from turning on until input voltage exceeds approximately 1.7v. if input voltage drops below approximately 1.3v, uvlo turns off the mosfet switch, flg will be asserted accordingly. under- voltage detection functions only when the chip enable input is enabled. current limiting and short-circuit protection the current limit circuitry prevents damage to the mosfet switch and external load. it is user adjust- able with an external set resistor, r set , i limit = 210k /r set in the range of 0.5a to 3a. the accuracy of current limit set point may vary with operating temperature and supply voltage. see ? typical operating characteristics ? graph for further details. d g s normal mosfet rt9703 d g s
rt9703 12 ds9703-09 april 2011 www.richtek.com the normal current limit value, i limit , is set with an external resistor between ip (pin 8) and gnd (pin 4). when a heavy load or short circuit is applied to an enabled switch, a large transient current may flow until the current limit circuitry responds. once this current limit threshold is exceeded, the device enters constant current mode until the thermal shutdown occurred or the fault is removed. it is important to note that the maximum current limit value shall be set properly in accordance with its supply voltage otherwise it may result in the failure occurrence. the graph below shows the maximum current limit and supply voltage on the safe operation area. thermal shutdown thermal shutdown is employed to protect the device from damage if the die temperature exceeds approximately 130 c. if enabled, the switch automatically restarts when the die temperature falls 10 c. the output and flg signal will continue to cycle on and off until the device is disabled or the fault is removed. power dissipation the device's junction temperature depends on several factors such as the load, pcb layout, ambient temperature and package type. the output pin of rt9703 can deliver a current of up to 3a over the full operating junction temperature range. however, the maximum output current must be derated at higher ambient temperature to ensure the junction temperature does not exceed 100 c. with all possible conditions, the junction temperature must be within the range specified under operating conditions. power dissipation can be calculated based on the output current and the r ds(on) of switch as below. p d = r ds(on) x i out 2 although the devices are rated for 3a of output current, but the application may limit the amount of output current based on the total power dissipation and the ambient temperature. the final operating junction temperature for any set of conditions can be estimated by the following thermal equation : p d(max) = ( t j(max) - t a ) / ja where t j(max) is the maximum junction temperature of the die (100 c) and t a is the maximum ambient temperature. the junction to ambient thermal resistance ( ja ) for sop- 8 package at recommended minimum footprint is 104 c/ w ( ja is layout dependent). supply filter/bypass capacitor a 10 f low-esr ceramic capacitor from v in to gnd (the amount of the capacitance may be increased without limit), located at the device is strongly recommended to prevent the input voltage drooping during hot-plug events. however, higher capacitor values will further reduce the voltage droop on the input. furthermore, without the bypass capacitor, an output short may cause sufficient ringing on the input (from source lead inductance) to destroy the internal control circuitry. an important note to be award of is the parasitic inductance of pcb traces can cause over-voltage transients if the pcb trace has even a few tens of nh of inductance. it is recommended to use aluminum electrolytic acted the supply capacitor to prevent the device from being damaged. the input transient must not exceed 6.5v of the absolute maximum supply voltage even for a short duration. maximun current limit vs. supply voltage 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 22.5 33.5 44.5 55.5 supply voltage (v) maximun current limit (a) a t a = 25 c
rt9703 13 ds9703-09 april 2011 www.richtek.com fault flag filtering (optional) the transient inrush current to downstream capacitance may cause a short-duration error flag, which may cause erroneous over-current reporting. a simple 1ms rc low- pass filter (10k and 0.1 f) in the flag line eliminates short-duration transients. pcb layout in order to meet the voltage drop, droop, and emi requirements, careful pcb layout is necessary. the following guidelines must be considered: z keep all input and output traces as short as possible and use at least 150-mil & 2 ounce copper for all races. z avoid vias as much as possible. if vias are necessary, make them as large as feasible. z place a ground plane under all circuitry to lower both resistance and inductance and improve dc and transient performance (use a separate ground and power plans if possible). z locate the bypass capacitors as close as possible to the input and output pin of the rt9703. gnd vout en vin ip flg gnd gnd board layout
rt9703 14 ds9703-09 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050

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